Data reuse analysis of local stereo matching

  title={Data reuse analysis of local stereo matching},
  author={Tsung-Hsien Tsai and Nelson Yen-Chung Chang and Tian-Sheuan Chang},
  journal={2008 IEEE International Symposium on Circuits and Systems},
External memory bandwidth and internal memory size have been major bottlenecks in designing VLSI architecture for real-time stereo matching hardware because of large amount of pixel data and disparity range. To address these bottlenecks, this work explores the impact of data reuse on disparity-order and pixel-order along with the partial column reuse (PCR) and vertically expanded row reuse (VERR) techniques we proposed. The analysis suggest that a disparity-order reuse with both PCR and VERR… CONTINUE READING
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