Corpus ID: 230437869

Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems

@article{Das2021DataCI,
  title={Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems},
  author={Abhijit Das and John Jose and Prabhat Mishra},
  journal={ArXiv},
  year={2021},
  volume={abs/2101.00055}
}
Multi-threaded applications are capable of exploiting the full potential of many-core systems. However, Networkon-Chip (NoC) based inter-core communication in many-core systems is responsible for 60-75% of the miss latency experienced by multi-threaded applications. Delay in the arrival of critical data at the requesting core severely hampers performance. This brief presents some interesting insights about how critical data is requested from the memory by multi-threaded applications. Then it… Expand

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References

SHOWING 1-10 OF 15 REFERENCES
The SPLASH-2 programs: characterization and methodological considerations
TLDR
This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality. Expand
Computer Architecture: A Quantitative Approach
This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most importantExpand
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks
TLDR
A slack-aware re-routing (SAR) technique that prioritises lower slack packets over higher slack packets and explores alternate minimal path when two no-slack packets compete for same output port is presented. Expand
Intel Xeon Phi Processor 7235
  • 2017
Knights Landing: Second-Generation Intel Xeon Phi Product
This article describes the architecture of Knights Landing, the second-generation Intel Xeon Phi product family, which targets high-performance computing and other highly parallel workloads. ItExpand
OpenPiton: An Open Source Manycore Research Framework
TLDR
OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor and framework that leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design. Expand
The runahead network-on-chip
TLDR
The Runahead NoC is proposed, a lightweight, lossy network that provides single-cycle hops that enables an extremely simple bufferless router microarchitecture that performs routing and arbitration within the same cycle as link traversal. Expand
Critical word forwarding with adaptive prediction
  • Apr. 29 2014, uS Patent 8,713,277.
  • 2014
Increasing cache capacity via critical-words-only cache
TLDR
A novel cache design known as the critical-words-only cache (co-cache) for increasing the effective cache capacity is proposed, which involves rethinking the notion of cache blocks; instead of storing all the words that belong to a cache block, they only store the critical words. Expand
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
  • B. Daya, C. Chen, +6 authors L. Peh
  • Computer Science
  • 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
  • 2014
TLDR
SCORPIO is presented, an ordered mesh Network-on-Chip (NoC) architecture with a separate fixed-latency, bufferless network to achieve distributed global ordering, designed to plug-and-play with existing multicore IP and with practicality, timing, area, and power as top concerns. Expand
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