DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability

@article{Gong2018DUOEO,
  title={DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability},
  author={Seong-Lyong Gong and Jungrae Kim and Sangkug Lym and Michael B. Sullivan and Howard David and Mattan Erez},
  journal={2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
  year={2018},
  pages={683-695}
}
DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to sparing, can resolve inherent faults without significant changes to DRAM, but it is inefficient for highly-reliable systems where rank-level ECC (RECC) is already used against operational faults. In addition, DRAM design in the near future (possibly as early as DDR5) may transfer data in longer bursts, which complicates… CONTINUE READING

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