DSP architecture for motion estimation acceleration

Abstract

A modified DSP architecture, to accelerate motion estimation (ME) algorithms, is presented in this paper. The proposed SIMD and VLIW architecture is a trade-off between ASIC implementation and DSP implementation of ME, which can perform subtract, absolute and add (SAA.) operations on 8 pixels and fetch 8 new pixels from memory at the same time. A flexible… (More)

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