DRAM-Aware Last-Level Cache Replacement

  title={DRAM-Aware Last-Level Cache Replacement},
  author={Chang Joo Lee and Eiman Ebrahimi and Veynu Narasiman and Onur Mutlu and Yale N. Patt},
The cost of last-level cache misses and evictions depend sig ificantly on three major performance-related characteristics of DRAM-based main memory systems: bank-level paral lelism, row buffer locality, and write-caused interferenc . Bank-level parallelism and row buffer locality introduce d ifferent latency costs for the processor to service misses: parallel or serial, fast or slow. Write-caused interference ca n cause writebacks of dirty cache lines to delay the service o f subsequent reads… CONTINUE READING