DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

  title={DIFMOS\&\#8212;A floating-gate electrically erasable nonvolatile semiconductor memory technology},
  author={W. M. Gosney},
  journal={IEEE Transactions on Electron Devices},
  • W. Gosney
  • Published 1 May 1977
  • Engineering
  • IEEE Transactions on Electron Devices
Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A… 

Figures and Tables from this paper

An Electrically Using Alterable Nonvolatile Memory Cell a Floating-Gate Structure
An electrically alterable, floating-gate, nonvolatile memory transistor has been developed, with a cell area of under 500 Urn*, and using an advanced n-channel, polysilicon gate process. Cell
Electrically alterable hot-electron injection floating gate MOS memory cell with series enhancement
An electrically alterable, floating gate, non-volatile memory transistor has been developed, having a cell area of under 500µ2, and using an advanced n-channel, polysilicon gate process. Cell
An electrically alterable nonvolatile memory cell using a floating-gate structure
Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuit design, and a 5-V, 16K high-speed EAROM has been developed which shows successful programming and erase behaviour at nominal voltages of 25 and 35 V.
A two-transistor SIMOS EAROM cell
A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate
Trimming analog circuits using floating-gate analog MOS memory
  • L. Carley
  • Engineering
    IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers
  • 1989
The author presents an analog trim-voltage memory (ATVM) which employs a floating-gate MOS structure similar to that used in digital electrically erasable and programmable read-only memories
A high-density, high-performance EEPROM cell
The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing
A hot-hole erasable memory cell
Electrical erasure of in-system memory chips has always been a desire for circuit operation. A novel technique which utilizes hot-hole injection in the snapback regime for memory erasure is
Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors
AbstractA proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build
Electrically alterable read-only memory cell with graded energy band-gap insulator
Low voltage alterability and excellent memory retention have been obtained with a novel EAROM cell that has a graded energy band-gap film as the first insulator of a Floating-Gate type memory. The
Fabrication Technology and Physical Fundamentals of Components Used for Semiconductor Memories
In the field of digital memories, semiconductors have become more and more important besides magnetics, although they have not been able to completely replace the latter so far. They received a


Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure
Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate
Atmos—An electrically reprogrammable read-only memory device
An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This
Characterization of thin-oxide MNOS memory transistors
A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation
Electrically reprogrammable nonvolatile semiconductor memory
Electrically reprogrammable nonvolatile memories using avalanche injection of electrons and holes into a floating gate are described and the results of measurement on fabricated devices are shown.
Memory Behavior in a Floating-Gate Avalanche-Injection MOS (famos) Structure
A novel charge‐storage structure is described. The floating‐gate avalanche‐injection MOS (FAMOS) structure is shown to exhibit memory behavior in the form of long‐term charge storage on the floating
A fully-decoded 2048-bit electrically-programmable MOS ROM
A novel MOS charge storage transistor developed for an electrically-programmable ROM will be described, which provides access times of 500 ns (dynamic mode) or 800 ns (static mode).
Effects of insulator thickness fluctuations on MNOS charge storage characteristics
The effects of insulator thickness fluctuations on the charge storage characteristics of MNOS direct tunneling devices were investigated, using capacitor structures carefully fabricated by depositing
Properties of MNOS structures
The properties of thin oxide MNOS structures are studied. An analytical theory for the switching time constant is derived and curves of the switching time constant versus the nitride field are