• Corpus ID: 16366449

DIAPRISM Hardware Sorter — Sort a Million Records Within a Second —

@inproceedings{Azuma2000DIAPRISMHS,
  title={DIAPRISM Hardware Sorter — Sort a Million Records Within a Second —},
  author={Shinsuke Azuma and Takao Sakuma and Tetsuya Takeo and Takaaki Ando and Ken Shirai},
  year={2000}
}
Mitsubishi Electric Corp. has released the DIAPRISM hardware sorter for OLAP (On-Line Analytical Processing) and data warehouse applications. It enables high-speed sorting on a commercial PC server. The sorter employs a pipeline merge sort algorithm. It consists of multiple sort processors connected linearly and necessary amount of memory for each processor. The architecture of the sort processor is capable of sorting 4GB of data at one time. The sorter has achieved Datamation benchmark record… 
research.microsoft.com
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References

SHOWING 1-5 OF 5 REFERENCES
GREO: a commercial database processor based on a pipelined hardware sorter
TLDR
The query processing model underlying GREO architecture is presented and its architectural features are described, and the experiences on making research results an actual commercial product are reported.
High-performance sorting on networks of workstations
We report the performance of NOW-Sort, a collection of sorting implementations on a Network of Workstations (NOW). We find that parallel sorting on a NOW is competitive to sorting on the large-scale…
A measure of transaction processing power
TLDR
These benchmarks measure the performance of diverse transaction processing systems and a standard system cost measure is stated and used to define price/performance metrics.
Millennium sort: a cluster-based application for windows NT using DCOM, river primitives and the virtual interface architecture
We present the design and results of Millennium Sort, a distributed sorting application built using three layers of technology: extensible River System primitives, the Virtual Interface Architecture…
High-Performance Sort Chip