Corpus ID: 212479177

DESIGN AND IMPLEMENTATION OF 31- ORDER FIR LOW-PASS FILTER USING MODIFIED DISTRIBUTED ARITHMETIC BASED ON FPGA

@inproceedings{Patel2013DESIGNAI,
  title={DESIGN AND IMPLEMENTATION OF 31- ORDER FIR LOW-PASS FILTER USING MODIFIED DISTRIBUTED ARITHMETIC BASED ON FPGA},
  author={Shrikant Patel},
  year={2013}
}
This paper provide the principles of Modified Distributed Arithmetic, and introduce it into the FIR filters design, and then presents a 31-order FIR low-pass filter using Modified Distributed Arithmetic, which save considerable MAC blocks to decrease the circuit scale, meanwhile, divided LUT method is used to decrease the required memory units and pipeline structure is also used to increase the system speed. The implementation of FIR filters on FPGA based on traditional method costs… Expand
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