DENA: A DVFS-Capable Heterogeneous NoC Architecture


The current design drivers for multi-cores, namely performance per watt, scalability and flexibility, make the Networks-on-Chip (NoCs) the de-facto on-chip interconnect. State of the art NoCs can exploit heterogeneous solutions and complex DVFS techniques to fulfill also the variability of the application requirements. Relevant showstoppers to the design of a truly flexible NoC fitting all the possible traffic conditions, are the burstiness of the traffic generated by modern applications magnified by the unbalanced usage of the interconnect resources due to the implemented coherence protocol. This paper presents DENA, a DVFS-capable, heterogeneous NoC design, encompassing the coherence protocol, the application behavior and the need to minimize the energy budget. Simulation results on a 64-core, 2D-mesh architecture executing the SPLASH2 benchmark suite, testify the advantages of DENA from both the performance and energy viewpoints with an average 34.3% energy-performance improvement against the state of the art DVFS-capable NoC design.

DOI: 10.1109/ISVLSI.2017.91

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Cite this paper

@article{Cremona2017DENAAD, title={DENA: A DVFS-Capable Heterogeneous NoC Architecture}, author={Luca Cremona and William Fornaciari and Andrea Marchese and Michele Zanella and Davide Zoni}, journal={2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, year={2017}, pages={489-494} }