DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout


In the MOS analog layout, variability suppression is becoming a major issue, as is layout efficiency. Introducing a transistor array (TA) style to analog layout, this article addresses the layout-dependent variability based on the measurement results of test chips on 90nm CMOS process. In TA style, a large transistor is decomposed into a set of unified… (More)
DOI: 10.1145/2888395

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