Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

@article{Dodiu2012CustomDC,
  title={Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation},
  author={Eugen Dodiu and Vasile Gheorghita Gaitan},
  journal={2012 IEEE International Conference on Electro/Information Technology},
  year={2012},
  pages={1-5}
}
System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses. If a part of the scheduling components or the entire functionality is moved from software to… CONTINUE READING
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Hard-Soft Real-Time Performance Evaluation of Linux RTAI Based Embedded Systems”, in Electronics and Electrical Engineering, Kaunas:Technologija

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Improving commercial RTOS performance using a custom interrupt management scheduling policy

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