Current calculation on VLSI signal interconnects

@article{Shao2005CurrentCO,
  title={Current calculation on VLSI signal interconnects},
  author={Muzhou Shao and Youxin Gao and Li-Pen Yuan and Hung-Ming Chen and Martin D. F. Wong},
  journal={Sixth international symposium on quality electronic design (isqed'05)},
  year={2005},
  pages={580-585}
}
With IC technology scaling down to nanometer sizes, the higher working frequency and smaller geometry drive the reliability of signal interconnects to be a critical challenge in VLSI design. Post-layout reliability verification is an effective solution to this challenge. However, the implementation of a full-chip verification on signal electromigration requires a huge number of interconnect current calculations. The dynamic current calculation methods established on time domain circuit… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-10 of 11 references

Keynote Speech

  • Gordon Moore
  • IEEE International Electronic Devices Meeting,
  • 1996
1 Excerpt

Trends for deep submicron VLSI and their implications for reliability

  • P. K. Chatterjee, W. R. Hunter, +5 authors Ping Yang
  • Proc. IEEE Intl. Reliability Physics Symp. ,
  • 1995
1 Excerpt

An electromigration failure model for interconnects under pulsed and bidirectional current stressing

  • Jiang Tao, Nathan W. Cheung, Chenming Hu
  • IEEE Trans. Electron Devices, vol.41,
  • 1994
1 Excerpt

Similar Papers

Loading similar papers…