Cu seed optimization for minimum pitch wiring in 10nm and beyond

@article{Silva2016CuSO,
  title={Cu seed optimization for minimum pitch wiring in 10nm and beyond},
  author={Adam da Silva and Prakash Periasamy and Jeric Sarad and Anbu Selvam K. M. Mahalingam and San Leong Liew and Craig Child},
  journal={2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)},
  year={2016},
  pages={147-148}
}
Technology scaling necessitates interconnect structures (metal and vias) in the back end of the line (BEOL) module to sub 50nm pitch. This presents significant challenges to the conventional metallization scheme, consisting of liner, seed deposition and Cu plating. Seed layer deposition particularly is quite challenged because of increasing aspect ratio… CONTINUE READING