Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology

Abstract

The impact of crosstalk on the delay was examined by measuring a test chip manufactured with a 0.13-/spl mu/m-node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: (1) consideration of degradation change dependent on relative-signal-arrival-time over a wide range, (2) static timing analysis (STA… (More)

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