Circuit performance is strongly impacted by environmental conditions under which the circuit operates. In this paper, a worst-case critical path delay analysis technique is presented to consider the inter-dependencies between dynamic power, operating temperature, leakage, power supply variations and circuit delay. To allow for a realistic worst-case analysis of the critical path delays, the dynamic power consumptions of the chip-level circuit blocks are first mapped to the across-chip temperature and leakage distributions. Then, the dependency of the power supply levels along the critical path on the dynamic power consumptions is determined efficiently by locally analyzing the power grid. Finally, the worst-case critical path delay is found by solving constrained nonlinear optimization problems under the user-specified chip power consumption constrains and bounds. These constraints and bounds can be used to represent correlations between switching activities of different circuit blocks, power estimation uncertainty or various power level settings. The proposed technique is demonstrated on several benchmark circuits for which large chip-level thermal models and power grids are efficiently solved to facilitate the required worst-case analysis.
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