Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff.

  title={Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff.},
  author={Gordon E. Moore},
  journal={IEEE Solid-State Circuits Newsletter},
  • G. Moore
  • Published 2006
  • Art
  • IEEE Solid-State Circuits Newsletter
Moore's theories about the future of transistor technology first appeared in Electronics magazine in April 1965. Termed a "law" years later by Caltech professor Carver Mead, Moore's Law went on to become a self-fulfilling prophecy. 

Figures from this paper

Sustaining Moore’s Law with 3D Chips
It is argued that 3D chips coupled with new computer architectures can keep Moore’s law on its traditional scaling path.
Simply Fabless!
  • R. Kumar
  • Business
    IEEE Solid-State Circuits Magazine
  • 2011
Vertical integration at the integrated device manufacturers (IDMs) has been a norm in the semiconductor industry for many years. More than 20% of worldwide semiconductor revenue now comes from
Seamlessly fused digital-analogue reconfigurable computing using memristors
This work introduces a new design paradigm where the analogue and digital worlds are seamlessly fused via memristors, enabling electronics with reconfigurability.
Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers
Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade
The Significant Bits Propagation Model in Fault-Tolerant System Design
A novel technique for mathematical modeling of significant digits propagation under the presence of errors based on Min-Plus algebra, which is chosen to formalize structural dependencies and leads to the significant reduction of unavoidable fault-tolerant hardware overhead.
Silicon Integrated Optics: Fabrication and Characterization
For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However,
Productive Design of Extensible On-Chip Memory Hierarchies
A general framework for context-dependent parameterization of any hardware generator is described, a specific set of Chisel libraries for generating extensible cache-coherent memory hierarchies are defined, and a methodology for decomposing high-level descriptions of cache coherence protocols into controller-localized, object-oriented transactions is provided.
Nanowire Transistors and RF Circuits for Low-Power Applications
The background of this thesis is related to the steadily increasing demand of higher bandwidth and lower power consumption for transmitting data. The work aims at demonstrating how new types of
Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach
This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension
Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suitin