Covert and Side Channels Due to Processor Architecture

@article{Wang2006CovertAS,
  title={Covert and Side Channels Due to Processor Architecture},
  author={Zhenghong Wang and Ruby B. Lee},
  journal={2006 22nd Annual Computer Security Applications Conference (ACSAC'06)},
  year={2006},
  pages={473-482}
}
  • Zhenghong Wang, R. Lee
  • Published 11 December 2006
  • Computer Science
  • 2006 22nd Annual Computer Security Applications Conference (ACSAC'06)
Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show how processor architecture features such as simultaneous multithreading, control speculation and shared caches can inadvertently accelerate such covert channels or enable new covert channels and side channels. We first illustrate the reality and severity of this problem by describing concrete attacks. We identify two… 

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References

SHOWING 1-10 OF 31 REFERENCES
Theoretical Use of Cache Memory as a Cryptanalytic Side-Channel
  • D. Page
  • Computer Science, Mathematics
    IACR Cryptol. ePrint Arch.
  • 2002
TLDR
An attack is described which encrypts 2 chosen plaintexts on the target processor in order to collect cache profiles and then performs around 2 computational steps to recover the key.
Cache Attacks and Countermeasures: The Case of AES
TLDR
An extremely strong type of attack is demonstrated, which requires knowledge of neither the specific plaintexts nor ciphertexts, and works by merely monitoring the effect of the cryptographic process on the cache.
CACHE MISSING FOR FUN AND PROFIT
TLDR
It is demonstrated that this shared access to memory caches provides not only an easily used high bandwidth covert channel between threads, but also permits a malicious thread to monitor the execution of another thread, allowing in many cases for theft of cryptographic keys.
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
TLDR
An infrastructure called HIDE (Hardware-support for leakage-Immune Dynamic Execution) which provides a solution consisting of chunk-level protection with hardware support and a flexible interface which can be orchestrated through the proposed compiler optimization and user specifications that allow utilizing underlying hardware solution more efficiently to provide better security guarantees.
Transparent Run-Time Defense Against Stack-Smashing Attacks
TLDR
Two new methods to detect and handle buffer overflow vulnerabilities in process stacks are presented that work with any existing pre-compiled executable and can be used transparently per-process as well as on a system-wide basis.
Towards Efficient Second-Order Power Analysis
TLDR
This work considers two variants of second-order differential power analysis: Zero-Offset 2DPA and FFT2DPA, and explores a couple of attacks that attempt to efficiently employ second- order techniques to overcome masking.
Cache-timing attacks on AES
TLDR
This paper demonstrates complete AES key recovery from known-plaintext timings of a network server on another computer and discusses several of the obstacles to constant-time high-speed AES software for common general-purpose computers.
Cryptanalysis of DES Implemented on Computers with Cache
TLDR
The results of applying an attack against the Data Encryption Standard (DES) implemented in some applications, using side-channel information based on CPU delay as proposed in (11), found that the cipher can be broken with 2 known plaintexts and 2 24 calculations at a success rate > 90%, using a personal computer with 600-MHz Pentium III.
On Boolean and Arithmetic Masking against Differential Power Analysis
TLDR
The present paper shows that the `BooleanToArithmetic' algorithm proposed by T. Messerges is not sufficient to prevent Differential Power Analysis and the 'ArithmeticToBoolean' algorithm is not secure either.
Towards a theory of software protection and simulation by oblivious RAMs
TLDR
This paper distill and formulate the key problem of learning about a program from its execution, and presents an efficient way of executing programs such that it is infeasible to learn anything about the program by monitoring its executions.
...
...