Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits

@inproceedings{Kuimicz1993CouplingAS,
  title={Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits},
  author={W. Kuimicz and W. Denisiuk and J. Gempel and Zbigniew Jaworski and Mariusz Niewczas and Arno Pfitzner and Elzbieta Piwowarska and W. Pleskazc and Adam Wojtasik},
  year={1993}
}
This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a processldevice simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented. 
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