Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs

Abstract

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order… (More)
DOI: 10.1002/cta.1939

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