Cost-effective approach for reducing soft error failure rate in logic circuits

@article{Mohanram2003CosteffectiveAF,
  title={Cost-effective approach for reducing soft error failure rate in logic circuits},
  author={Kartik Mohanram and Nur A. Touba},
  journal={International Test Conference, 2003. Proceedings. ITC 2003.},
  year={2003},
  volume={1},
  pages={893-901}
}
  • K. Mohanram, N. Touba
  • Published 6 November 2003
  • Computer Science
  • International Test Conference, 2003. Proceedings. ITC 2003.
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is… 

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