# Cost-effective approach for reducing soft error failure rate in logic circuits

@article{Mohanram2003CosteffectiveAF, title={Cost-effective approach for reducing soft error failure rate in logic circuits}, author={Kartik Mohanram and Nur A. Touba}, journal={International Test Conference, 2003. Proceedings. ITC 2003.}, year={2003}, volume={1}, pages={893-901} }

In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is…

## 308 Citations

Partial error masking to reduce soft error failure rate in logic circuits

- Computer ScienceProceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems
- 2003

A new methodology for designing logic circuits with partial error masking is described, which uses two reduction heuristics to reduce the soft error failure rate significantly with a fraction of the overhead required for conventional TMR.

RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits

- Computer Science, Engineering2009 22nd International Conference on VLSI Design
- 2009

Experimental results indicate that RADJAM optimized logic circuits can reduce soft error rates by around 39% with marginal delay, area and power overheads.

Gate Sizing to Radiation Harden

- Engineering
- 2006

A gate-level radiation hardening technique for cost- effective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asym- metric…

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

- EngineeringIEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2013

The proposed soft error rate (SER) reduction framework, based on redundancy addition and removal (RAR), aims at eliminating those gates with large contribution to the overall SER, and integrates a resizing strategy into the framework, as post-RAR additive SER optimization.

Gate sizing to radiation harden combinational logic

- EngineeringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 2006

A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described, which uses a novel gate (transistor) sizing technique that is both efficient and accurate.

A LOW-COST, SYSTEMATIC METHODOLOGY FOR SOFT ERROR ROBUSTNESS OF LOGIC CIRCUITS

- Engineering
- 2015

Due to current technology scaling trends such as shrinking feature sizes and decreasing supply voltages, circuit reliability is becoming more susceptible to radiation-induced transient faults (soft…

Analysis of the soft error susceptibility and failure rate in logic circuits

- EngineeringInt. Arab J. Inf. Technol.
- 2011

This work analyzes the susceptibility of logic circuits to transient pulses through an extensive set of logic synthesis experiments and reveals that the SER is strongly correlated with logical masking of transient pulses and, thus, fast logic-level soft error failure rate assessment methods can be used in place of computationally-intensive circuit-level assessment techniques.

Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires

- Computer ScienceIEEE Transactions on Reliability
- 2008

It is demonstrated that the addition of functionally redundant wires reduces the probability that a single-event transient (SET) error will reach a primary output, and, by extension, the soft error rate (SER) of the circuit.

Modeling and Optimization for Soft-Error Reliability of Sequential Circuits

- Computer ScienceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 2008

Two approaches to evaluating the susceptibility of sequential circuits to soft errors are presented, one of which uses the Markov chain theory but can only provide steady-state behavior information, and the other uses symbolic modeling based on binary decision diagrams/algebraic decision diagrams and circuit unrolling.

Combinational logic soft error analysis and protection

- Engineering12th IEEE International On-Line Testing Symposium (IOLTS'06)
- 2006

It is shown on ISCAS '85 benchmarks that it is possible to reduce the soft error sensitivity by more than 60% at the cost of 20% in area with a design solution using only standard library cells, and the proposed method benefits from the smaller feature sizes of newer IC process technologies.

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