Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits

  title={Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits},
  author={Kartik Mohanram and Nur A. Touba},
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is… CONTINUE READING
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