Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits

@inproceedings{Mohanram2003CostEffectiveAF,
  title={Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits},
  author={Kartik Mohanram and Nur A. Touba},
  booktitle={ITC},
  year={2003}
}
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is… CONTINUE READING
Highly Influential
This paper has highly influenced 21 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 356 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 212 extracted citations

Transient fault characterization in dynamic noisy environments

IEEE International Conference on Test, 2005. • 2005
View 5 Excerpts
Highly Influenced

Soft error modeling and remediation techniques in ASIC designs

Microelectronics Journal • 2010
View 4 Excerpts
Highly Influenced

Modeling and Optimization for Soft-Error Reliability of Sequential Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2008
View 5 Excerpts
Highly Influenced

356 Citations

0204060'03'06'10'14'18
Citations per Year
Semantic Scholar estimates that this publication has 356 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 32 references

Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,

P. Shivakumar
Proc. International Conference on Dependable Systems and Networks, • 2002
View 3 Excerpts
Highly Influenced

Developing Standard Cells for TSMC 0.25μ Technology under MOSIS DEEP Rules”, Department of Electrical and Computer Engineering, Virginia

J. B. Sulistyo, D. S. Ha
2002

Analysis of SingleEvent Effects in Combinational Logic-Simulation of the AM2901 Bitslice Processor

Massengill 00 L.W. Massengill
IEEE Trans. Nuclear Science, • 2000
View 1 Excerpt

Cosmic Ray Neutron Multiple-Upset Measurements in a 0.6-/spl mu/m CMOS Process,

Hazucha 00a P. Hazucha, C. Svensson
IEEE Trans. Nuclear Science, • 2000

Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate,

Hazucha 00b P. Hazucha, C. Svensson
IEEE Trans. Nuclear Science, • 2000

Soft error considerations for deep-submicron CMOS circuit applications

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) • 1999
View 1 Excerpt

Similar Papers

Loading similar papers…