Correctly rounded floating-point division for DSP-enabled FPGAs

  title={Correctly rounded floating-point division for DSP-enabled FPGAs},
  author={Bogdan Pasca},
  journal={22nd International Conference on Field Programmable Logic and Applications (FPL)},
Floating-point division is a very costly operation in FPGA designs. High-frequency implementations of the classic digit-recurrence algorithms for division have long latencies (of the order of the number fraction bits) and consume large amounts of logic. Additionally, these implementations require important routing resources, making timing closure difficult in complete designs. In this paper we present two multiplier-based architectures for division which make efficient use of the DSP resources… CONTINUE READING
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