Copper filling of TSVs for interposer applications

  title={Copper filling of TSVs for interposer applications},
  author={Nils Jurgensen and Q. H. Huynh and Gunter Engelmann and H.-D. Ngo and Oswin Ehrmann and K. Lang and Albrecht Uhlig and T. Dretschkow and Dirk Rohde and O. Worm and Cornelia Jager},
  journal={2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)},
For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at… CONTINUE READING