Copper Wafer Bonding

  title={Copper Wafer Bonding},
  author={Andy Fan and A. Rahman and Rafael Reif},
  journal={Electrochemical and Solid State Letters},
Technology, performance, and computer-aided design of three-dimensional integrated circuits
The overall 3D integration process flow is discussed, as well as specific technological challenges and the issues they present to circuit designers and how these issues may be tackled during the placement, routing, and layout stages of physical design.
A novel approach for forming ductile Cu-to-Cu interconnection
Three-dimensional integrated-circuit (3D IC) is one of the most important electronic packaging technologies nowadays. Cu-to-Cu through-silicon-via interconnection is a crucial process in 3D IC.
Trend and Prospect for 3Dimensional Integrated-Circuit Semiconductor Chip
As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the
Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging
  • Electronic Packaging Science and Technology
  • 2021
Bonding Strength Evaluation of Copper Bonding Using Copper Nitride Layer
The recent semiconductor packaging technology is evolving into a high-performance system-in-packaging (SIP) structure, and copper-to-copper bonding process becomes an important core technology to
Effects of two-step plasma treatment on Cu and SiO2 surfaces for 3D bonding applications
Cu-to-Cu bonding is necessary for high density, fine-pitch interconnect and high bandwidth in 3D stacking technology. Although various Cu-to-Cu bonding studies have been reported so far, few