Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths

@article{Diken2014ConstructionAE,
  title={Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths},
  author={Erkan Diken and Roel Jordans and Rosilde Corvino and Lech J{\'o}zwiak and Henk Corporaal and Felipe Augusto Chies},
  journal={Microprocessors and Microsystems - Embedded Hardware Design},
  year={2014},
  volume={38},
  pages={947-959}
}
Numerous applications in important domains, such as communication and multimedia, show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may… CONTINUE READING
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