Automating hardware design at higher levels of abstraction requires first and foremost a formal model of the high-level specification. This formal model is the basis of many EDA applications such as synthesis, analysis or verification. It should have a compact form, but still be close to the original description. In this paper, we propose using a Data-Flow-Graph (DFG) as a formal model. We present a new approach for generating a DFG from a high-level C++ specification based on symbolic simulation. The main advantage of using symbolic simulation for this task is that conceptually all C++ constructs can be handled. No restriction to a subset of constructs is required. Furthermore, our approach focuses on the quality of the resulting DFG. It attempts to minimize the number of nodes while still producing DFGs that adhere to the original specification.