Constrained clock shifting for field programmable gate arrays

@inproceedings{Singh2002ConstrainedCS,
  title={Constrained clock shifting for field programmable gate arrays},
  author={D. Singh and S. Brown},
  booktitle={FPGA '02},
  year={2002}
}
Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting… Expand
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