Constrained clock shifting for field programmable gate arrays

  title={Constrained clock shifting for field programmable gate arrays},
  author={D. Singh and S. Brown},
  booktitle={FPGA '02},
Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting… Expand
29 Citations
Latch-Based Performance Optimization for Field-Programmable Gate Arrays
  • Bill Teng, J. Anderson
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2013
  • 6
Latch-Based Performance Optimization for FPGAs
  • Bill Teng, J. Anderson
  • Computer Science
  • 2011 21st International Conference on Field Programmable Logic and Applications
  • 2011
  • 9
  • PDF
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew
  • 11
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches
  • 27
  • PDF
Stratix™ 10 High Performance Routable Clock Networks
  • 11
  • Highly Influenced
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits
  • 18
  • PDF