Considerations on system-level behavioural and structural modeling extensions to VHDL

@article{Ashenden1998ConsiderationsOS,
  title={Considerations on system-level behavioural and structural modeling extensions to VHDL},
  author={P. Ashenden and P. Wilsey},
  journal={Proceedings International Verilog HDL Conference and VHDL International Users Forum},
  year={1998},
  pages={42-50}
}
  • P. Ashenden, P. Wilsey
  • Published 1998
  • Computer Science
  • Proceedings International Verilog HDL Conference and VHDL International Users Forum
This paper reviews the requirements on a language for modeling behaviour and structure at the system level, and considers possible approaches to extending VHDL to meet these requirements. Modeling issues in a system-level design language are identified, including abstraction of data, concurrency, communication and timing, and design refinement. Some system-level design languages and notations are surveyed, and previous proposals to extend VHDL for system-level design are reviewed. Specific… Expand
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