Congestion-Driven Global Placement for Three Dimensional VLSI Circuits


The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, the problem of thermal dissipation is magnified due to the nature of these layered technologies. In this paper, we develop techniques to reduce both the local and global congestions of 3D circuit designs in order to alleviate thermal issues. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local congestion. Then, we perform simulated annealing to reduce the circuit’s global congestion. Experimental results show that our local congestion is reduced by an average of over 44% and global congestion is reduced by over 16%. Moreover, we only see an 11% increase in the wiring length and the number of vias required.

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@inproceedings{Nanda2003CongestionDrivenGP, title={Congestion-Driven Global Placement for Three Dimensional VLSI Circuits}, author={Vidit Nanda and Karthik Balakrishnan and Mongkol Ekpanyapong and Sung Kyu Lim}, year={2003} }