Configuration Code Generation and Optimizations for Heterogeneous Reconfigurable Dsps

  title={Configuration Code Generation and Optimizations for Heterogeneous Reconfigurable Dsps},
  author={Suet-Fei Li and Marlene Wan and Jan Rabaey},
In this paper we describe a code generation and optimization process for reconfigurable architectures targeting digital signal processing and wireless communication applications. The ability to generate efficient and compact code is essential for the success of reconfigurable architectures. Otherwise, the overhead of reconfiguring could easily become the system bottleneck. Our code generation process includes the evaluation a set of tradeoffs in system design, software engineering as well as… CONTINUE READING


Publications referenced by this paper.
Showing 1-9 of 9 references

An Energy Conscious Methodology for Early Design Exploration of Heterogeneous DSPS

  • M. Wan, D. Lidsky, Y. Ichikawa, J. Rabaey
  • Proceedings of the Custom Integrated Circuit…
  • 1998
Highly Influential
3 Excerpts

Evaluation of a Low-Power Reconfigurable DSP Architecture

  • A. Abnous
  • Proceedings of the Reconfigurable Architecture…
  • 1998
1 Excerpt

Ultra-Low-Power Domain-Specific Multimedia Processors

  • A. Abnous, J. Rabaey
  • Proceedings of the IEEE VLSI Signal Processing…
  • 1996
1 Excerpt

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