Concurrent sizing, Vdd and V/sub th/ assignment for low-power design

  title={Concurrent sizing, Vdd and V/sub th/ assignment for low-power design},
  author={A. Srivastava and D. Sylvester and D. Blaauw},
  journal={Proceedings Design, Automation and Test in Europe Conference and Exhibition},
  pages={718-719 Vol.1}
  • A. Srivastava, D. Sylvester, D. Blaauw
  • Published 2004
  • Engineering
  • Proceedings Design, Automation and Test in Europe Conference and Exhibition
  • We present a sensitivity-based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on… CONTINUE READING
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