Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation

@article{Lu2013ConcurrentAC,
  title={Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation},
  author={Weiyun Lu and Martin Radetzki},
  journal={Microprocessors and Microsystems - Embedded Hardware Design},
  year={2013},
  volume={37},
  pages={115-128}
}
In this work, we present extensions to the SystemC library and automatable model transformations that enable efficient system-level fault simulation in SystemC. The method is based on extended data types which represent variables or signals as lists of values (instead of one value) consisting of a fault free reference value and any number of faulty values each of which corresponds to one fault. We inject faults (variable level faults as well as bit level faults) into objects declared with the… CONTINUE READING