Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme

@article{Lee2010ConcurrentED,
  title={Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme},
  author={Chiou-Yng Lee and Che Wun Chiou and Jim-Min Lin},
  journal={Journal of Signal Processing Systems},
  year={2010},
  volume={58},
  pages={233-246}
}
Successful implementation of elliptic curve cryptographic systems primarily depends on the efficient and reliable arithmetic circuits for finite fields with very large orders. Thus, the robust encryption/decryption algorithms are elegantly needed. Multiplication would be the most important finite field arithmetic operation. It is much more complex compared to the finite field addition. It is also frequently used in performing point operations in elliptic curve groups. The hardware… 
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB
  • Chiou-Yng Lee, Jiafeng Xie
  • Computer Science
    2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
  • 2019
TLDR
A novel fault detection scheme for finite field multipliers over GF(2m) with high fault detection capability and low-complexity implementation that can be extended further in many cryptographic applications is proposed.
Self-Checking Gaussian Normal Basis Multiplier over GF(2m) Using Multiplexer Approach
TLDR
The proposed SCAL GNB multiplier using multiplexer approach is with both concurrent error detection and off-line testing capabilities and can save about 18% space complexity as compared to existing similar study.
A Secure Modular Division Algorithm Embedding with Error Detection and Low-Area ASIC Implementation
TLDR
A modular division algorithm embedding with error detection is proposed that not only greatly reduces the area overhead of modular division but also improves the security of modulardivision implementation.
Fault-tolerant Gaussian normal basis multiplier over GF(2m)
TLDR
The proposed fault-tolerant GNB multiplier with type-t can tolerate at most t/2-1 failed modules simultaneously, while existing GNB multipliers with CEC only can tolerate one failed module.
Self-checking alternating logic bit-parallel gaussian normal basis multiplier with type-t
TLDR
The proposed SCAL GNB is the first normal basis multiplier to have both on-line error-detection and off-line testing capabilities, and can detect both permanent and transient faults.
Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept
TLDR
A new low-cost technique, for fault-localization and error-correction, which utilizes the self-dual concept in binary signed-digit adders, whereas previous approaches were unable to localize and correct with 100 % reliability even with longer time durations and greater hardware cost.

References

SHOWING 1-10 OF 29 REFERENCES
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)
TLDR
In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2m) according to the Fenn’s multiplier, and shows that all single stuck-at faults can be detected concurrently.
Fault Detection Architectures for Field Multiplication Using Polynomial Bases
TLDR
New architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two are proposed.
Concurrent Error Detection in Montgomery Multiplication over GF(2m)
TLDR
This paper will design a Montgomery multiplier array with a bit-parallel architecture in GF(2m) with concurrent error detection capability to protect it against fault-based attacks.
On Concurrent Detection of Errors in Polynomial Basis Multiplication
TLDR
Experimental results presented here show that due to an increase in the number of parity bits, the area overhead tends to increase linearly, but the probability of error detection approaches unity fairly quickly, e.g., for eight parity bits.
Low complexity word-level sequential normal basis multipliers
TLDR
Two classes of architectures for multipliers over the finite field GF(2/sup m/) are proposed, which are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multipliers available in the open literature.
Improved VLSI designs for multiplication and inversion in GF(2/sup M/) over normal bases
  • Lijun Gao, G. Sobelman
  • Computer Science
    Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)
  • 2000
TLDR
Improved VLSI designs for computing multiplication and inverse in GF(2/sup m/) over normal bases are presented and the latency of the inversion method is reduced with parallelism exploration at no cost in hardware.
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
TLDR
It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads, so for large values of m these overheads are particularly low.
A New Construction of Massey-Omura Parallel Multiplier over GF(2m)
TLDR
It is shown that, not only does this type of multiplier contain redundancy in that special class of finite fields, but it also has redundancy in fields GF(2/sup m/) defined by any irreducible polynomial, and a new architecture for the normal basis parallel multiplier is proposed, which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original Massey-Omura normal basis Parallel multiplier.
An Efficient Optimal Normal Basis Type II Multiplier
TLDR
This paper presents a new parallel multiplier for the Galois field GF(2/sup m/) whose elements are represented using the optimal normal basis of type II, and the time complexities of the proposed and the Massey-Omura multipliers are similar.
Multiplexer-based array multipliers
A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient
...
...