Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs


We propose a concurrent error detection (CED) scheme for a network of combinational logic blocks implemented with memory embedded in FPGAs. The proposed scheme is proven to detect - without latency - any permanent or transient fault associated with a single input or output of any component of the network. The experimental results show that the overhead for… (More)
DOI: 10.1109/DSD.2008.31


6 Figures and Tables

Slides referencing similar topics