Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs

Abstract

A concurrent error detection (CED) scheme for combinational logic blocks implemented with embedded memory blocks (EMBs) available in today's FPGAs is proposed. The scheme guarantees the detection of each permanent or transient fault resulting in a single-bit error at the input or output of any component of the circuit. Extensions of the basic scheme aimed… (More)
DOI: 10.1109/DDECS.2008.4538760

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Cite this paper

@article{Krasniewski2008ConcurrentED, title={Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs}, author={Andrzej Krasniewski}, journal={2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems}, year={2008}, pages={1-6} }