Concurrency and Hardware Design

@inproceedings{Cortadella2002ConcurrencyAH,
  title={Concurrency and Hardware Design},
  author={Jordi Cortadella and Alexandre Yakovlev and Grzegorz Rozenberg},
  booktitle={Lecture Notes in Computer Science},
  year={2002}
}
We introduce a simple formal framework for specifying and implementing concurrent systems. The framework enables the specification of safety and progress properties and is based on Enhanced Characteristic Functions. The use of Enhanced Characteristic Functions leads to simple definitions of operations such as hiding and various process compositions. We discuss two compositions: the network composition for building networks of processes and the specification composition for building… 
Comparison of Different Algorithms to Synthesize a Petri Net from a Partial Language
TLDR
Two new algorithms that effectively synthesize a finite place/transition Petri net (p/t-net) from a finite set of labeled partial orders (a finite partial language) are presented.
Performance Evaluation of Process Partitioning Using Probabilistic Model Checking
TLDR
A probabilistic state exploration method to evaluate a priori the efficiency of a set of partitions in terms of the speedup they achieve for a given model and shows that it is quite effective in identifying partitions that result in better levels of parallelism.
RECONFIGURABLE LOGIC CONTROLLER FOR EMBEDDED APPLICATIONS
TLDR
Refined, structured and verified description of Reconfigurable Logic Controller is mapped directly into FPGA by means of using dedicated and commercial synthesis tools.
Semantic Heterogeneity in the Formal Development of Complex Systems: An Introduction
TLDR
This work states that there are currently no generally applicable tools for dealing with the heterogeneity of interactions in the engineering of complex systems.
ANALYSIS OF SAFENESS, LIVENESS AND PERSISTENCE PROPERTIES OF PETRI NETS BY MEANS OF MONOTONE LOGIC FUNCTIONS
TLDR
The algorithm of symbolic analysis of a Petri net based behavioural specification of logic controllers is given, together with conditions, which allow analysing the properties of safeness, liveness and persistence properties of Petri nets.
Determinate STG Decomposition of Marked Graphs
TLDR
It is proved that for live marked graphs — a subclass of Petri nets of definite practical importance in the area of circuit design — the decomposition result depends only on the signal partition, and characterise redundant places in these marked graphs as shortcut places.
Synthesis of Asynchronous Hardware from Petri Nets
TLDR
These new methods avoid using full reachability state space for logic synthesis and include direct mapping of Petri nets to circuits, structural methods with linear programming, and synthesis from unfolding prefixes using SAT solvers.
The conception of concurrent Petri net and its synthesis
TLDR
Proposed concurrent PT net expand possibility of functional model dealing by invariant combinations of weights structures by treating placements in standard connections with input and output system transitions.
Models from Scenarios
TLDR
This paper presents a survey on the technique of region based synthesis of Petri nets from languages, where each word in a given language specifies one run of the searched Petri net.
Combining Decomposition and Unfolding for STG Synthesis
TLDR
A combined approach to alleviate the state space explosion problem, based on using Petri net unfoldings and decomposition is presented, which shows significant improvement in terms of runtime compared with other existing methods.
...
1
2
...

References

SHOWING 1-10 OF 55 REFERENCES
Concurrent hardware : the theory and practice of self-timed design
The Models of Parallel Processes Specification and the Behaviour of the Circuits Verification of Parallel System Behaviour Through Formal Models The Relationship between the State and Event Models
Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design)
TLDR
This paper provides an overview of petrify and the theory behind its main functions and shows how back-annotating to the specification level helps the designer to control the design process.
A structural encoding technique for the synthesis of asynchronous circuits
TLDR
A novel synthesis method based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed, which opens the door to the synthesis of large control specifications generated from hardware description languages.
Structural methods for the synthesis of speed-independent circuits
TLDR
Experimental results show that circuits can be generated from specifications that exceed in several orders of magnitude the largest STGs ever synthesized-with over 10/sup 27/ states, and computation times are also dramatically reduced.
Synthesis of self-timed VLSI circuits from graph-theoretic specifications
TLDR
This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs), and develops a number of analytical results which establish the equivalence between the static structure of nets and their underlying firing sequence semantics.
Timing analysis of asynchronous circuits using timed automata
TLDR
These results, combined with recent results concerning the analysis and synthesis of timed automata, provide for the systematic Treatment of a large class of problems that could be treated by conventional simulation methods only in an ad-hoc fashion.
Automatic Verification of Timed Circuits
TLDR
A new formalism and a new algorithm for verifying timed circuits that allows hierarchical verification based on a behavioral semantics of timed trace theory are presented and results demonstrate that this verification algorithm is practical for realistic examples.
Modular Design of Asynchronous Circuits Defined by Graphs
  • R. David
  • Computer Science
    IEEE Transactions on Computers
  • 1977
TLDR
This paper presents the principle of the CUSA and the synthesis method using flow tables, an original method which enables one to reduce the number of cells and useful connections and is adapted to a synthesis from a flow graph.
ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS
TLDR
This thesis presents results on structural constraints guaranteeing global operation, and decompositions of complex systems into meaningful parts, and for a corresponding class of systems called Production Schemata.
Representing and modeling digital circuits
TLDR
This dissertation concerns the development and exploration of one such design representation of orbital nets and shows how it is appropriate for a wide range of circuit design tasks, and discovers some new techniques for specification, modeling, simulation, and verification of circuits.
...
1
2
3
4
5
...