Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

  title={Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors},
  author={Rajeev R. Rao and Kaviraj Chopra and David Blaauw and Dennis Sylvester},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs. In this paper, we present a fast and efficient soft error rate (SER) analysis methodology for combinational circuits. We first present a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit. We then describe the construction of the descriptor object that efficiently captures the correlation between the… CONTINUE READING
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Impact of CMOS technology scaling on atmospheric neutron soft error rate

  • P. Hazucha, C. Svensson
  • IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2586…
  • 2000
Highly Influential
5 Excerpts

MARS-C: Modeling and analysis of soft errors in combinational circuits

  • N. Miskov-Zivanova, D. Marculescu
  • Proc. DAC, Jul. 2006, pp. 767–772.
  • 2006
1 Excerpt

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