Recursive Pseudo-Exhaustive Two-Pattern Generation
Design automation is a challenge for tool designers, due to increasing complexity of building VLSI circuits with molecular and nano-scale precision. Recent emerging complex problems in the field of VLSI design can be easily solved through the divide and conquer approach using partitioning methods. Although, partitioning problem has major importance in the field of VLSI design automation, it is treated with a testing perspective in this paper. This facilitates to address the reliability and testability issues of VLSI systems during the early product development stages. An automated VLSI design tool for partitioning combinational CMOS circuits that can create parallel testable VLSI circuits, is developed and discussed. This computer aided tool can optimize the design constraints of test time and hardware overhead for design-for-testability (DFT) by an exploration of the solution search space. After partitioning and optimization, a considerable reduction in the length of test vectors is obtained.