Corpus ID: 37640785

Compressor Based Area-Efficient Low-Power 8 x 8 Vedic Multiplier

@inproceedings{Pokhriyal2013CompressorBA,
  title={Compressor Based Area-Efficient Low-Power 8 x 8 Vedic Multiplier},
  author={Nidhi Pokhriyal and Harsimranjit Kaur and N. R. Prakash},
  year={2013}
}
Multipliers are the integral components in the design of many high performance FIR filters, image and digital signal processors. Multipliers being the most area and power consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, multiplier based on ancient Vedic mathematics technique has been proposed which employs 4:3, 5:3, 6:3 and 7:3 compressors for addition of partial products. Combining the Vedic SutraUrdhwa Tiryakbhyam and efficient… CONTINUE READING
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References

SHOWING 1-6 OF 6 REFERENCES
A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors
  • 59
  • PDF
Design and implementation of two variable multiplier using KCM and Vedic Mathematics
  • L. Sriraman, T. N. Prabakar
  • Mathematics, Computer Science
  • 2012 1st International Conference on Recent Advances in Information Technology (RAIT)
  • 2012
  • 58
Performance comparison review of 32-bit multiplier designs
  • K. Swee, Lo Hai Hiung
  • Computer Science
  • 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)
  • 2012
  • 27
Low-power 4-2 and 5-2 compressors
  • K. Prasad, K. Parhi
  • Computer Science
  • Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)
  • 2001
  • 128
  • PDF
Low power CMOS pass logic 4-2 compressor for high-speed multiplication
  • D. Radhakrishnan, A. Preethy
  • Mathematics
  • Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)
  • 2000
  • 105
  • PDF
Multiplier design based on ancient Indian Vedic Mathematics
  • 202