• Corpus ID: 37640785

Compressor Based Area-Efficient Low-Power 8 x 8 Vedic Multiplier

@inproceedings{Pokhriyal2013CompressorBA,
  title={Compressor Based Area-Efficient Low-Power 8 x 8 Vedic Multiplier},
  author={Nidhi Pokhriyal and Harsimranjit Kaur and Neelam Rup Prakash},
  year={2013}
}
Multipliers are the integral components in the design of many high performance FIR filters, image and digital signal processors. Multipliers being the most area and power consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, multiplier based on ancient Vedic mathematics technique has been proposed which employs 4:3, 5:3, 6:3 and 7:3 compressors for addition of partial products. Combining the Vedic SutraUrdhwa Tiryakbhyam and efficient… 

Tables from this paper

Area-efficient low PDP 8-bit vedic multiplier design using compressors

  • Harsimranjit KaurN. R. Prakash
  • Computer Science
    2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS)
  • 2015
TLDR
A novel higher-order compressor based 8-bit Vedic multiplier, which shows substantial improvement in area, speed and Power Delay Product when compared with existing designs.

An Efficient Implementation of High Speed Vedic Multiplier Using Compressors for Image Processing Applications

TLDR
This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders that results in faster edge detection and is 2 times speedier than a ‘simple’ multiplier.

Area Efficient Low Power Compressor Design Using GDI Technique

TLDR
The proposed compressors show reduction in area and power ranging from 38.8% to 65.26% and 33.3% to 40% respectively when compared with CMOS based compressors.

Area Efficient Low Power Vedic Multiplier Design Using GDI Technique

TLDR
A power efficient technique, Gate Diffusion input, has been used to design all the leaf cells of the multiplier and when compared with CMOS based multiplier, the proposed multiplier shows 36.05% reduction in area and 31% reduced in power.

Implementation of Multipliers using Stacker Based Binary Compressors

  • S. KN. S. Murty
  • Computer Science, Engineering
    2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)
  • 2018
TLDR
Design of 6:3 and 7:3 binary compressors using 3-bit stacker circuit is proposed and shows 14% and 23% decrease in delay and 6% and 17% decreases in power respectively, when compared with the basic compressor designs which use full adders and half adders.

A SURVEY ON HIGH SPEED VEDIC MATHEMATICS MULTIPLIER USING COMPRESSORS

TLDR
A novel architecture capable of performing high speed multiplication with the help of vedic mathematics is discussed, along with which 4:2 compressors and 7:1 compressors are used for the purpose of addition.

Performance comparison review of 8–3 compressor on FPGA

TLDR
Seven compressors designed with adder circuits or multiplexer circuits were implemented in Altera EP2C70F896 FPGA and their performance compared in terms of number of logic gates used, cell area and power delay product (PDP) for an optimum recommendation for the implementation of 8–3 compressor design in FPGa.

Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder

TLDR
The work has proved that area and delay of proposed Vedic multiplier are less than existing Vedic multipliers.

III . Design of Proposed Reversible Logic Mux-Multiplier ( RlMM ) 3

TLDR
The novel concept of RLMM is introduced in designing multiplier for edge detection of face images using reversible logic gates and the performance of the proposed method is better compared to existing methods.

Demystification of Vedic Multiplication Algorithm

TLDR
This novel approach, i.e., finding algorithm from the end results of conventional calculations may be useful in devising algorithms similar to Vedic in cases of other calculations.

References

SHOWING 1-6 OF 6 REFERENCES

A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

TLDR
A 16×16 bit multiplier has been developed using special kind of adders that are capable to add five/six/seven bits per decade and Binary counter property has been merged with the compressor property to develop high order compressors.

Design and implementation of two variable multiplier using KCM and Vedic Mathematics

  • L. SriramanT. Prabakar
  • Mathematics
    2012 1st International Conference on Recent Advances in Information Technology (RAIT)
  • 2012
TLDR
A novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed, which is similar to that of a Constant Co-efficient Multiplier (KCM), but for KCM one input is to be fixed, while the proposed multiplier can multiply two variables.

Performance comparison review of 32-bit multiplier designs

  • K. SweeLo Hai Hiung
  • Computer Science
    2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)
  • 2012
TLDR
This study of a relative performance comparison of various 32-bits multiplier designs of Array, Wallace, Dadda, Reduced Area and Radix-4 Booth Encoding multipliers in the Area- Optimized, Speed-Optimized and Auto-optimized synthesis modes in Leonardo Spectrum concluded that Radix -4 BoothEncoding multiplier has the best findings in the area performance.

Low-power 4-2 and 5-2 compressors

  • K. PrasadK. Parhi
  • Computer Science, Engineering
    Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)
  • 2001
TLDR
This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units, which are building blocks for binary multipliers.

Low power CMOS pass logic 4-2 compressor for high-speed multiplication

A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate is used to build the circuit while totally eliminating the use of inverters. The total power

Multiplier design based on ancient Indian Vedic Mathematics

Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). It mainly deals with Vedic