Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time

@article{Hu2005CompressionscanCF,
  title={Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time},
  author={Yu Hu and Xiaowei Li and Xiaoqing Wen},
  journal={11th Pacific Rim International Symposium on Dependable Computing (PRDC'05)},
  year={2005},
  pages={8 pp.-}
}
Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and… CONTINUE READING