Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy

@inproceedings{Smith2003CompletionCompletenessFN,
  title={Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy},
  author={Scott C. Smith},
  booktitle={VLSI},
  year={2003}
}
Delay-Insensitive paradigms, such as NULL Convention Logic (NCL), require an additional condition, referred to herein as Completion-Completeness, in order to ensure delay-insensitivity when the bit-wise completion strategy is used along with one or more components that are not complete with respect to all of their inputs. Completion-completeness requires that completion signals only be generated such that no two adjacent DATA wavefronts can interact within any combinational component. Correctly… CONTINUE READING