Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache

@inproceedings{Li2012CompilerassistedPC,
  title={Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache},
  author={Qing'an Li and Mengying Zhao and Chun Jason Xue and Yanxiang He},
  booktitle={LCTES},
  year={2012}
}
As technology scales down, energy consumption is becoming a big problem for traditional SRAM-based cache hierarchies. The emerging Spin-Torque Transfer RAM (STT-RAM) is a promising replacement for large on-chip cache due to its ultra low leakage power and high storage density. However, write operations on STT-RAM suffer from considerably higher energy consumption and longer latency than SRAM. Hybrid cache consisting of both SRAM and STT-RAM has been proposed recently for both performance and… CONTINUE READING
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