Comparison of passive and active pixel schemes for CMOS visible imagers

  title={Comparison of passive and active pixel schemes for CMOS visible imagers},
  author={Lester J. Kozlowski and J. Luo and William E. Kleinhans and T. Liu},
  booktitle={Defense, Security, and Sensing},
An active pixel sensor (APS) integrated in standard CMOS process technology is shown to be superior to an alternative passive pixel sensor (PPS). Further, the CMOS APS provides video sensitivity and SNR comparable to CCDs. Though the CMOS PPS has lower performance, it offers >50% optical fill factor without microlenses and can be produced at lower cost for applications not requiring broadcast quality SNR (>35 dB) under low light conditions (<20 lx). APS and PPS SNRs of 50 dB and 44 dB are… 
Theoretical basis and experimental confirmation: why a CMOS imager is superior to a CCD
Sub-micron CMOS has already enabled the development of IR focal plane array with ultra-low read noise and high sensitivity for many demanding applications. The successful monolithic integration of
Proposal and Preliminary Experiments of Dynamic Range Extension Method for CMOS Imagers by Hybrid Use of Active and Passive Pixel Readout Schemes
A dynamic range extension method for CMOS imagers with an in-pixel lateral overflow structure, in which one of active and passive readout schemes is selected at each pixel on the basis of the illumination, and an image reproduction scheme that makes use of electric calibration from a pixel-wise mixed-mode image.
A self-calibrating single-chip CMOS camera with logarithmic response
A high-dynamic-range CMOS image sensor consisting of nonintegrating, continuously working photoreceptors with logarithmic response is presented. The nonuniformity problem caused by the
CMOS passive pixel image design techniques
We 0hWr hwe9sbv s1 M if pWTn s*kn to reproduce nd t dftbute WuW papr and 09ect rn coes of thi k dbcum,.iwn v b or in pat. Abstract CMOS technology provides an attractive alternative to the currently
Sigma-delta A/D converter for CMOS image sensors
The comparison between the solution presented here and other solutions show that the circuit complexity is similar but the performance, in terms of signal to noise ratio, is superior.
Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35µm Process
An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip.
Progress toward high-performance infrared imaging systems-on-a-chip
Continuing advances in CMOS technology including finer lithography, the addition of dense planarized interconnect layers, concomitant improvements in transistor performance, and the availability of
Deep Trench Isolation and Inverted Pyramid Array Structures Used to Enhance Optical Efficiency of Photodiode in CMOS Image Sensor via Simulations
The photodiode in the backside-illuminated CMOS sensor is modeled to analyze the optical performances in a range of wavelengths to highlight the effectiveness of various DTI and d combinations on the OEs and evaluate the OE difference between the pixel arrays with and without the DTI + IPA structures.
Pixel Readout Circuit for X-Ray Imagers
This paper describes the per-pixel readout circuit of an X-ray imaging matrix and compares it to other solutions. The per-pixel readout circuit consists of a digital pixel sensor array constituted by
Simulation models for photogate active pixel sensor
The constant reduction in the transistors sizes for the design and the integration of smart sensors on chip requires accurate simulations of electrical characteristics. To this end, new simulation


A low-noise Bi-CMOS linear image sensor with auto-focusing function
A bipolar imaging device consisting of a capacitor-loaded emitter follower circuit for a phototransistor has been implemented in a linear image sensor with two lines of 48-bit array for an autofocus
Design consideration and performance of a new MOS imaging device
The design considerations and performance of a new MOS imaging device with novel random noise suppression (RANS) circuits are described. This device consists of 492 × 388 photodiodes, a vertical
Integrated arrays of silicon photodetectors for image sensing
Development of linear and area arrays of silicon photodetectors operating in a photon flux integration mode is described. This mode of operation, which permits the trade of gain for bandwidth, is
MOS area sensor: Part II&#8212;Low-noise MOS area sensor with antiblooming photodiodes
The development of a high-sensitivity 320 × 244 element MOS area sensor and a novel fixed pattern noise (FPN) suppressing circuit are reported in this paper. The new device incorporates p+-n+high-C
Low-noise capacitive transimpedance amplifier performance versus alternative IR detector interface schemes in submicron CMOS
  • L. Kozlowski
  • Environmental Science
    Defense, Security, and Sensing
  • 1996
We compare the capacitive transimpedance amplifier (CTIA) to two other IR detector interface circuits using data compiled from hybrid FPAs in various formats from 8 X 8 to 1024 X 1024. The CTIA
Storage mode operation of a phototransistor and its adaptation to integrated arrays for image detection
It will be shown that a phototransistor possesses all the necessary requirements to operate in a photon flux integration mode; i.e. 1) a storage element, 2) a nearly ideal switch, and 3) a current
Low-noise performance and dark-current measurements on the 256 x 256 NICMOS3 FPA
The NICMOS3 infrared focal plane array (FPA), which was designed as a Hubble Telescope upgrade device, provides excellent low-noise images in the 1 - 2.5 micrometers (SWIR) band. Both the detector
MOS area sensor: Part I&#8212;Design consideration and performance of an n-p-n structure 484 &#215; 384 element color MOS imager
The design consideration and performance of an n-p-n structure 484 × 384 element MOS imager is described. The imager has a photodiode array and scanners separately integrated on different p wells.
HgCdTe 20482 FPA for infrared astronomy: development status
The HAWAII-2 is an IR 20482 focal plane array (FPA) that is being developed for next-generation IR astronomy. It will supplant our HAWAII 10242 as the largest high- performance imaging array
MOS electronics for a portable reading aid for the blind
A unique direct-translation reading aid for the blind has been realized with two custom MOS integrated circuits that achieve reading rates in excess of 80 words per minute, indicating that the system may become widely used by the blind.