Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems Domino logic circuits are used which reduce sub-threshold leakage current in standby mode and improve noise immunity for wide OR gates. In this paper we analyze and compare different domino logic design topologies for lowering the sub-threshold leakage current in standby mode, increasing the speed and increasing the noise immunity. We compare power, delay, and unit noise gain (UNG) of different topologies. The simulation results revealed that High Speed Clock Delay Domino (HSCD) circuit gives the better results in terms of reduction in delay and power consumption as compare to other circuits.