Comparative analysis of a 2-bit magnitude comparator using various high performance techniques

Abstract

This brief summarizes the comparative analysis of a 2 bit Magnitude Comparator using different techniques. A comparator forms a fundamental element which is used in the complex arithmetic and logical circuitry that involves the comparison of n-bit numbers. Various high performance methods which are aimed at enhancing the performance statistics are simulated at 45nm technology using Tanner EDA Tool. The derived results are compiled in this brief. A novel approach derived from the comparative analysis, based on Hybrid PTL/CMOS logic style has shown best results and has been proposed towards the end.

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Cite this paper

@article{Sharma2015ComparativeAO, title={Comparative analysis of a 2-bit magnitude comparator using various high performance techniques}, author={Geetanjali Sharma and Hiten Arora and Jitesh Chawla and Juhi Ramzai}, journal={2015 International Conference on Communications and Signal Processing (ICCSP)}, year={2015}, pages={0079-0083} }