Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits

@article{Mostafa2009ComparativeAO,
  title={Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits},
  author={Hassan Mostafa and Mohab Anis and Mohamed I. Elmasry},
  journal={2009 IEEE Computer Society Annual Symposium on VLSI},
  year={2009},
  pages={133-138}
}
In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed… CONTINUE READING
Highly Cited
This paper has 18 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 12 extracted citations

Comparative analysis of process variation impact on flip-flops soft error rate

2009 1st Asia Symposium on Quality Electronic Design • 2009
View 3 Excerpts
Highly Influenced

The impact of timing yield improvement under process variation on flip-flops soft error rate

2009 1st Asia Symposium on Quality Electronic Design • 2009
View 6 Excerpts
Highly Influenced

References

Publications referenced by this paper.
Showing 1-10 of 13 references

Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic for High Performance Processors,

F. Klass
IEEE Journal of Solid-State Circuits, • 1999
View 4 Excerpts
Highly Influenced

Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance

2007 IEEE International Symposium on Circuits and Systems • 2007
View 6 Excerpts
Highly Influenced

Challenge: variability characterization and modeling for 65- to 90-nm processes

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005. • 2005
View 2 Excerpts

Effects of Parameter Variations on Timing Characteristics of Clocked Registers,

P. R. Gada, W. R. Roberts, D. Velenis
International Conference on Electro Information Technology, • 2005
View 1 Excerpt

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. • 2005
View 1 Excerpt

On the need for statistical timing analysis

Proceedings. 42nd Design Automation Conference, 2005. • 2005
View 1 Excerpt

Statistical timing based optimization using gate sizing

Design, Automation and Test in Europe • 2005
View 1 Excerpt

Design and reliability challenges in nanometer technologies

Proceedings. 41st Design Automation Conference, 2004. • 2004
View 1 Excerpt

Similar Papers

Loading similar papers…