Compact modeling of on-chip ESD protection devices using Verilog-A

  title={Compact modeling of on-chip ESD protection devices using Verilog-A},
  author={Junjun Li and S. Joshi and R. Barnes and E. Rosenbaum},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON… CONTINUE READING
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