Compact Designs of SubBytes and MixColumn for AES

  title={Compact Designs of SubBytes and MixColumn for AES},
  author={C. Nalini and P. V Anandmohan and D. V Poomaiah and Vivek D. Kulkarni},
  journal={2009 IEEE International Advance Computing Conference},
The most critical factors responsible for bottleneck in the design and implementation of high-speed AES (Advanced Encryption Standard) architectures for any resource constrained target platform such as an FPGA are Substitute byte/Inverse SubstituteByte and MixColumn/InverseMixcolumn operations. Most implementations conventionally make use of the memory intensive look up table approach for Substitute byte/Inverse SubstituteByte (SB/ISR) block implementations resulting in an unbreakable delay… CONTINUE READING