Combining internal scan chains and boundary scan register: A case study

Abstract

The paper presents a Design-For-Testability (DFT) approach for System-on-Chips (SOC) that combines internal scan chains and boundary scan register (BSR) into a single scan register known as Scan-Through-TAP (STT) methodology. We are using the IEEE Standard 1149.1 Instruction as a user defined instruction (UDI) to control the internal scan chains operation… (More)

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