Combating NBTI Degradation via Gate Sizing

@article{Yang2007CombatingND,
  title={Combating NBTI Degradation via Gate Sizing},
  author={Xiangning Yang and Kewal K. Saluja},
  journal={8th International Symposium on Quality Electronic Design (ISQED'07)},
  year={2007},
  pages={47-52}
}
NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies. We believe that designers can combat NBTI degradation using appropriate circuit constraints. This paper presents a design technique to tolerate NBTI degradation by gate sizing. We provide an NBTI-aware gate sizing problem formulation and propose a solution method. The experimental results for MCNC'91 benchmark circuits show that for NBTI tolerance the purposed method results in less than 1% area… CONTINUE READING
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